1. Field of the Invention
The present invention relates to high speed, parallel data processing systems and, more particularly, to a parallel data processor comprised of an array of identical, uniquely constructed and interconnected cells which perform arithmetic and logical data processing functions under the control of a master controller.
2. State of the Prior Art
Parallel data processors typically employ a number of identical processing cells arranged in a matrix-like array so that data can be processed in parallel. The usual parallel processor consists of a n by m identical cells each connected to its immediately neighboring cells and each controlled by a central controller. This approach is particularly suited for processing data matrices of the types encountered in high resolution image processing. A description of one such processing array and its many applications in data processing is set forth in Holsztynski et al. patent No. 4,215,401.
The basic structure of each cell of the processor described in the Holsztynski et al. patent includes a random access memory (RAM), a single bit input accumulator, a single bit output accumulator and a NAND gate processing element. The RAM, the input terminal of the input accumulator, the output terminal of the output accumulator and one input terminal of the NAND gate are connected to a data bus. The output signal from the input accumulator is supplied to the second input terminal of the NAND late which has its output terminal connected to the input terminal of the output accumulator.
With a plurality of identical cells of this type interconnected with neighboring cells and a central controller, the parallel processor described in this patent can be programmed to rapidly perform a variety of elemental logical functions on large amounts of data. Combinations of these elemental functions by proper program sequences allow the processor to perform more complex logical and even arithmetic functions.
While the parallel processor shown in the foregoing patent permits the construction of large arrays and thus parallel processing of large data matrices, the use of a NAND gate as the processing element and the arrangement of the storage elements in relation to the NAND gate result in a requirement for relatively complex sequences of program instructions and some loss of speed when performing complex logical and arithmetic functions. Holsztynski et al. recognized that the addition of more complex processing elements such as full adders to the disclosed NAND gate processor embodiment would increase data processing speed. However, such addition of elements to the processor cell also would result in considerably increased complexity and cost, particularly for large arrays.
This combination of a logic element to perform logical functions and a full adder to perform arithmetic functions in a processing cell for a parallel processor was also suggested in a paper by John H. Smit of Goodyear Aerospace entitled "Architecture Description For The Massively Parallel Processor (MPP) And The Airborne Associative Processor (ASPRO)", prepared for the Very High Speed Computing Symposium, Sept. 9-10, 1980 at Georgia Institute of Technology. The processor cell disclosed in the Smit paper includes various registers and logic elements for "logic and routing" functions. A full adder, shift register and single bit registers are used for "bit-serial arithmetic" operations. As suggested in the Holsztynski et al. patent, this arrangement speeds up the processing of data by providing separate logic and arithmetic sections. Again, however, the complexity and cost factors are considerably greater than with the NAND gate processing arrangement of Holsztynski et al.